A block diagram of the complete ZX SPECTRUM micro-computer is given below, click on the picture for a bigger version. It is valid for all build standards, fitted with either 16k or 48k bytes of dynamic RAM memory. Although functionally identical, detailed circuit changes have been introduced to improve reliability and to assist with manufacture. The printed circuit board layout has also been modified. Details of these changes are highlighted where necessary in the following paragraphs, and in later sections referring to fault diagnosis and repair.
The architecture of the Spectrum shown above is typical of many microcomputer systems in that it comprises a single microprocessor board (in this instance a Z80A or u780 CPU), a read only memory (ROM), an expandable RAM memory and an input/output section handling the keyboard, tape and TV display functions. The latter is recognisable as the logic gate array (ULA) and the three functional blocks shown in the right of the diagram.
The computer is built on a single printed circuit board which also includes a regulated power supply fed from an external 9V power pack. The keyboard matrix is part of the upper case assembly and is connected to the board via two ribbon cables KB1 and KB2. A description of each section follows.
The Z80A is an 8-bit single-IC central processing unit (CPU). It is clocked at 14.0 MHz from an external source controlled by the logic gate array (ULA) and has a standard three bus input/output arrangement. These buses are the Data Bus, Address Bus and Control Bus respectively.
D7-D10 constitutes an 8-bit bi-directional data bus with active high, tri-state input/outputs. It is used for data exchanges with the memory and with the ULA.
A15-A0 constitutes a 16-bit address bus with active high, tri-state outputs. The address bus provides the address for memory (up to 64k bytes) data exchanges and for data exchanges with the ULA. It is also used during the interrupt routine when scanning the keyboard matrix.
The control bus is a collection of individual signals which generally organise the flow of data on the address and data buses. The block diagram only shows five of these signals although others of minor importance are made available at the expansion port.
Starting with memory request (MREQ), this signal is active low indicating when the address bus holds a valid address for a memory read or memory write operation. Input/Output request (IORQ) is also active low but indicates when the lower half of the address bus holds a valid I/O address for the ULA during I/O read/write operations.
The read and write signals (RD and WR) are active low, and one or other is active indicating that the CPU wants to read or write data to a memory location or I/O device. All the control signals discussed so far are active low, tri-state outputs.
The last control signal described here is the maskable interrupt (INT). This input is active low and is generated by the ULA once every 20ms. Each time it is received the CPU `calls` the `maskable interrupt` routine during which the real-time is incremented and the keyboard is scanned.
Returning to the CPU clock mentioned earlier in this section, the ULA is able to inhibit this input bringing the CPU to a temporary halt. This mechanism gives the ULA absolute priority, allowing it to access the standard 16k RAM without interference from the CPU (see RAM description). Switching transistor TR3 ensures that the clock amplitude is +5V rather than some arbitrary TTL level. This is essential if the CPU is to operate effectively while executing fast machine code programs of the `space invader` type.
Dynamic Memory Refresh
The CPU incorporates built-in dynamic RAM refresh circuitry. As part of the instruction OP code fetch cycle, the CPU performs a memory request after first placing the refresh address on the lower eight bits of the address bus. At the end of the cycle the address is incremented so that over 255 fetch cycles, each row of the dynamic RAM is refreshed. This mechanism only applies to the optional 32k expansion RAM in the the 48k Spectrum. An alternative refresh method is adapted for the standard 16k RAM.
In the standard 16k Spectrum there are 32k bytes of addressable memory equally divided between ROM and RAM.
The lower 16k bytes of memory (addresses 0000 - 3FFF) are implemented in a single ROM (IC5) which holds the monitor program. This program is a complex Z80 machine code program divided broadly into three parts one each covering the input/output routines, the BASIC interpreter and expression handling. Details of the program content, although outside the scope of this manual, are referred to as necessary.
The upper 16 bytes of memory (addresses 4000 - 7FFF) are implemented using eight 16k bit dynamic RAMs (IC6-IC13). Approximately half of this space is available to the user for writing BASIC or machine code programs, The remainder is used to hold the system variables including 6k bytes reserved for the memory mapped display area.
In the 48k Spectrum an additional 32k bytes of RAM are provided (addresses 8000 - FFFF) which are implemented using eight 32k bit dynamic RAMs (IC15-IC32). The RAM, providing extra memory space for the user, is normally fitted during manufacture but may be added retrospectively using the RAM expander kit. In addition to the RAMs, the kit includes the address multiplexer and read/write control ICs IC23-IC26. Board space and the necessary discrete components are already provided on the board.
The following description should be read in conjunction with the ciruit diagrams.
Read Only Memory (IC5)
The CPU addresses the ROM directly during memory read cycles using the address bus A13-A0. MREQ and RD enable the ROM and the ROM outputs respectively. A third input (CS) derived by the ULA (ROMCS) selects the ROM, provided the higher order address bits A14 and A15 are both low. These are reserved for accessing the RAM memory which starts with address 4000 (ie address A14 set). An external ROM IC select input, supplied via the expansion port on pin 25A, selectively disables the on-board ROM by pulling the select input high. By virtue of R33 placed on the ULA side of the ROM the ULA ROMCS output is effectively inhibited. Interface 1 uses this mechanism allowing the CPU to read the extension ROM in the interface for microdrive and RS232 applications.
Links H and N, shown directly above IC5, allow a second source ROM to be fitted. The Hitachi (H) and NEC (N) ROMs use different pins for the enable and select inputs (ie pins 20 and 27). The links allow the inputs to be reversed accordingly.
Standard 16k RAM (IC6-IC13)
The eight 16k RAM ICs making up the standard 16k x 8 bit RAM memory are organised as a matrix of 128 rows x 128 columns. Thus, separate 7-bit row and column addresses are required to access any one of the locations. These addresses are supplied by the CPU on address bus A13-A0 via an address muliplexer IC3/IC4. The low order address bits A6-A0 give the row address and are selected at the beginning of the memory access cycle when initially the RAS output from the ULA is high. Later, as the row address is latched, RAS goes low selecting the high order address bits A13-A7 giving the column address.
The RAS/CAS outputs from the ULA are generated in sequence in response to MREQ and A14 from the CPU. The DRAMWE output, also from the ULA is a decode of the RD/WR waveforms telling the RAM to expect either a read or write cycle.
It is also apparent from the circuit diagram that the ULA can access RAM by generating a set of addresses independent of those generated by the CPU. The address port for the RAM is therefore dualled by the insertion of small value resistors (R17-R23) on the address multiplexer side of the RAM. This ensures that where there is likely to be conflict between the ULA and CPU, the ULA address has priority. Priority is assigned on the basis that the ULA must access the memory mapped display area in the RAM at set intervals in order to build up the video for the TV display. If the ULA is about to access the RAM and it detects either A14 or A15 (ie the CPU is also about to access the RAM) the ULA inhibits the CPU clock temporarily halting the CPU memory transaction until its own transaction is completed.
Resistors R1 to R8, in series with the data bus lines, perform a similar function to the address port resistors described above. They ensure that the ULA does not `see` CPU write data while the ULA is accessing the RAM.
Refresh for the standard 16k dynamic RAM is accomplished during normal read cycles, ie most rows are refreshed each time the ULA accesses the memory mapped displayed area during picture compilation; the remaining rows are refreshed as a result of other read cycles also known to occur at regular intervals within the refresh period.
32k Expansion RAM (IC15-IC32)
The eight 32k ICs making up the 32k x 8 bit expansion RAM are in fact 64k ICs with either row or column drop-out rendering one hald of the memory non-functional. In order to accommodate the Texas Instruments RAM (Type TMS 4532) or the optional OKI RAM (Type MSM3732) a set of links are provided, visible on the circuit diagram above the address multiplexer IC25/IC26. These links not only cater for the different manufacturer (Issue 3 Spectrums only) but also allow, in both instances, one of the two IC versions to be selected depending on which half of the RAM (top, bottom, left or right) is functional. The links are respectively TI and OKI (manufacturer - Issue 3 Spectrums only), -3/-4 (TI version) and -H/-L (OKI version - Issue 3 Spectrums only).
It is essential when replacing ICs in this area that all RAMs carry the same manufacturers part number and that all links are selected accordingly.
The expansion RAM is organised as a matrix of 128 rows x 256 columns (TI RAMs) or 256 rows x 128 (OKI RAMs). Thus, seperate 7/8 bit row and column addresses are required to access any of these locations. These addresses are supplied by the CPU on address bus A14-A0 via an address multiplexer IC25/IC26. For example, when accessing the TI RAM the low order address bits A6 to A0 give the row address; AR is held low on the -3 version selecting the top half of the memory and high on the -4 version selecting the bottom half. The column address is given by the high order address bits A14-A7.
Row/column address selection and RAS/CAS timing for the RAM is decoded in IC23/IC24 from inputs supplied by the CPU, ie address line A15 selecting addresses 8000 upwards, and MREQ heralding a memory read or write cycle. A theoretical timing diagram is show below.
The input/output section of the Spectrum is centered round the ULA (IC1). The functions performed within the device include TV video compilation, keyboard scanning and tape input/output. It also derives and controls the CPU clock (CPU) using an external 14 MHz crystal X1, and drives the loudspeaker when a `BEEP` instruction is being executed. Each of these sections and the supporting circuits are described below.
The video compilation section of the ULA operates in conjunction with the memory mapped picure display area in the standard 16k RAM, the colour (chrominance) modulator (IC14) and the UHF modulator. This combination produces a high resolution, 24 line x 32 character, eight colour TV display.
Using the 14 MHz clock the ULA derives line and field timing compatible with the external TV receiver. Video is derived by accessing the memory mapped display area in the RAM in a set sequence at set times throughout the picture frame. The addresses are necessarily independent of the CPU and appear on the ULA address lines A6 through A0 as two seperate bytes timed by the RAS/CAS row/column address select lines.
The net result is three seperate video waveforms outputs from the ULA on pins 15, 16 and 17. These carry the luminence signal Y, incorporating the line and field sync, and two unmodulated colour difference signals U and Y making the Spectrum compatible with both colour and monochrome receivers.
From the ULA the colour difference signals are applied to the colour modulator IC14 via two level shifting networks. These match the ULA output levels with those required by the B-Y and R-Y inputs to the modulator. In the Issue 2 Spectrum the level shifting network is passive, incorporating two potentiometers VR1, VR2. These are required to set-up the chroma bias level on IC14 pin 3 such that the voltage difference measured between pin 3 and the colour difference signals on pins 2 and 3 respectively in nominally 0V dc. In the Issue 3 Spectrum two active networks incorporating TR8 and TR9 eliminate the potentiometers, greatly improving colour stability.
The level shifted colour difference signals, input to IC14, are then encoded, by quadrature modulating two 4.43 MHz chroma sub-carriers. The sub-carriers are generated with the assistance of an external crystal X2 and a CR lead/lag network introducing a 90 degrees phase shift between pins 1 and 18. (A further difference between the Issue 2 and 3 Spectrums lies in the bias oscillator. The early issues incorporate a trimmer TC2 allowing the chroma sub-carrier frequency to be adjusted; on the later issues the frequency is fixed). The resultant modulated colour difference signals are finally mixed producing a composite chroma sub-carrier at IC14 pin 13.
At this point the chroma signal is ac coupled to the base of TR2 and added to the inverted luminence signal on TR1 collector. The resultant composite video is then buffered and applied to an encapsulated UHF modulator operating on European standard channel 36.
Every 20ms (ie once per maskable interrupt), the CPU systematically scans the keyboard recording which keys (if any) have been pressed. The scanning method is described below with the aid of the diagram below. As the diagram clearly illustrates the keyboard consists of an 8 x 5 matrix, the inter-section of each row and column bridged by a normally open switch contact. The row `outputs` and column `inputs` are shown connected by separate ribbon cables KB1 and KB2, one to the ULA and the other to the high order address lines A15-A8. Pull-up resistors R64 through R68 ensure that when the address bus is in the high Z state, or none of the key-switches is closed, row outputs KB0 to KB4 remain high.
When the keyboard scanning routines are entered the CPU performs successive I/O read cycles setting the IOREQ and RD lines to the ULA, low. At the same time, the I/O port addresses placed on the upper half of the address bus are modified with each cycle such that each of the address lines A15 through A8 is set low in turn, the other lines remain high.
The sequence starts with I/O port address FE driving address line A8 low. The keyboard matrix also sees this potential on column 6 applied via D6 and the ribbon cable KB2. Thus, when any of the switches on the inter-section with column 6 is pressed, the corresponding row output supplying the ULA vis the second ribbon cable (KB1), is pulled low. The row signal(s) is subsequently inverted by the ULA and placed on one of the five low order data bus lines. For example, if the CAPS SHIFT key is pressed row one output drives data bus D0 high and so on. The sequence ends with I/O address 7F when column 8 is addressed. In this instance, operation of the SPACE key drives D0 high. Clearly, the keyboard scanning routines make the distinction between the CAPS SHIFT and SPACE key by knowing which address line is being driven.
When LOADing or SAVEing programs using a cassette recorder, the ULA transfers information between the MIC and EAR sockets and the data bus, performing A/D and D/A conversions as required. Since the LOAD and SAVE functions are mutually exclusive, a single pin on the ULA (ie pin 28) is used both for input and output. Separate I/O read/write cycles to port address 254 configure the pin accordingly. During the LOAD operation the CPU executes successive I/O read cycles, reading the EAR input off data dus 6. When performing a SAVE operation, the CPU executes successive I/O write cycles, this time writing data to the MIC output via data bus 3.
To ensure that I/O cycles are correctly implemented, the IOREQ line supplying the ULA is gated with address line A0 via TR6. Thus, if any memory transactions occur where A0 is high (ie not port address 254) then the IOREQ input is forced high inhibiting any attempt to perform an I/O cycle.
Loudspeaker (BEEP) Operation
It should be noted that while SAVEing the level of the MIC output is barely sufficient to drive the loudspeaker via D9 and TR7 (D10). However, during the execution of a BEEP instruction the CPU writes instead to port 254 on data bus 4. This effectively boosts the MIC output, driving the loudspeaker so that the BEEP tone can be easily heard. During the execution of such an instruction the cassette recorder is not running so there is no conflict at the MIC/EAR sockets.
The on-board power supply unit requires a 9V unregulated supply from the external Sinclair ZX power pack and derives the following internal supply rails.
The external power pack incorporates a mains transformer, full wave rectifier and capacitive smoothing. A thermal fuse is fitted at the transformer input.
The on-board power supply unit incorporates a 7805 regulator, deriving the +5V power rail, and an inverter stage TR4/TR5. The latter raises the level of the +9V unregulated supply to in excess of +12V. The resultant square wave at the junction of TR4 collector and the inverter coil is subsequently rectified and smoothed by D5/C44 producing the +12V output for the RAM. Additional smoothing, imparted by R62/C45, produces the +12V supply for the TV circuits free from noise generated by the RAM, and is available at the expansion port for use by peripherals. The +12V, +5V and -5V are also made available.
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